The use of scan registers is a common design methodology for digital circuits that simplifies testing of manufactured integrated circuit (IC) semiconductor chips. Particularly, when a plurality of flip flops are used for a counter, a register or a like element on a semiconductor chip—a test for confirmation of operation of the flip flops themselves must be performed. Since a test of each flip flop requires a large circuit scale by a test circuit, a plurality of flip flops are combined to form a shift register for testing and a shifting operation of the shift register is confirmed to effect a test of the component flip flops. Generally, in a semiconductor integrated circuit formed on a semiconductor chip, from the point of view of design efficiency, basic circuits such as flip flops which compose the circuit are registered as cells in a library and layout design is performed by reference to the cells in the library. Traditionally, the cells of flip flops are divided into cells of the LSSD type and cells of the mux-D type, among other things.
Traditionally, the cells of flip flops are divided into cells of the LSSD type and cells of the mux-D type. IBM developed several full serial integrated scan architectures, referred to as Level-Sensitive Scan Design (LSSD). FIG. 1 illustrates a block diagram of a prior art LSSD design that uses a polarity-hold, hazard-free, and level-sensitive latch. When a clock is enabled, the state of a latch is sensitive to the level of the corresponding data input. To obtain race-free operation, clocks C and B as well as A and B are nonoverlapping.
A cell of a flip flop of the LSSD type includes a first selector for selecting one of a system clock and a first clock (A clock) in response to a selection signal, an inverter for inverting the system clock, a second selector for selecting one of an output signal of the inverter and a second clock (B clock) in response to the selection signal, a third selector for selecting one of a data signal and a scanning signal in response to the selection signal, a first latch circuit formed from a transmission gate or a like element for inputting an output of the fist selector as a clock and latching an output signal of the third selector at a rising edge of the clock, and a second latch circuit formed from a transmission gate or a like element for inputting an output of the second selector as a clock and latching an output of the first latch circuit.
Further, an output of the flip flop of the LSSD type is inputted as a scanning signal to another flip flop in the following stage while the system clock, A clock, and B clock are inputted commonly to construct a large shift register composed of several shift registers. A scanning signal is inputted from the outside to the top one of the flip flops of the shift register to form the large shift register.
FIG. 2 illustrates a block diagram of a prior art mux-D cell. A cell of the mux-D type includes an inverter for inverting a system clock in response to a selection signal, a first selector (e.g., scan-enable) for selecting one of a data signal and a scanning signal in response to the selection signal, and a second latch circuit formed from a transmission gate or a like element for inputting the system clock as a clock and latching an output signal of the first selector at a rising edge of the clock. Further, an output of the flip flop of the mux-D type is inputted as a scanning signal to another flip flop in the following stage while the system clock is inputted commonly to construct a shift register. A scan-enable signal is inputted from the outside to the top of the flip flops of the shift register to form a register. Mux-D scan registers are a popular scan style that uses a shift-enabled control signal to configure scan registers into one or more scan chains during scan-mode. Any desired test vector can be shifted-in in scan-mode, and the values stored in the scan registers are shifted out from the other end of the scan chain.
Where flip flops of the mux-D type are used, while there is an advantage that the circuit scale is smaller than that where flip flops of the LSSD type are used, there is a drawback. Because the system clock is also used for the scan operation, and different flip-flops may have different system clock signals that may experience timing skew that can corrupt the shifting process.